As Moore's Law pushes device densities to over 100 million transistors per chip, and mixed-mode analog and digital designs are implemented, some design teams are now able to implement full products on a single chip. Such designs combine an array of disparate "blocks", or subsystems, and bring all interconnect busses on-chip, for higher speed and lower power dissipation. The single-chip implementation should also be the lowest-cost way to achieve the product's function. Though this approach seems inevitable, there are a number of significant challenges affecting implementation. The major one, at this time, appears to be our ability to test these complex chips.
This two-day course introduces the student to the field of SoC (System-on-Chip) DFT (Design For Testability) and ATPG (Automatic Test Pattern Generation). The course is divided into three parts: Test Synthesis, ATPG, and BIST (Built-In Self Test).
In Part I, we present the overall SoC design methodology. Both Logical and Physical Design flows are analyzed and then complemented with an overview of DFT (Design For Test) techniques, Test Synthesis and tester interfaces. This includes detailed analysis of the industry's leading DFT methodology, called Scan Design.
In Part II, we present an overview of the manufacturing test. The different types of failures that occur during the wafer's manufacturing process will be discussed, as well as the various leading fault models used to represent these failures. This includes the most popular Stuck-At fault model, the Path Delay model and the IDDQ testing model. Next, we explain how test vectors can be generated automatically using ATPG, and we'll analyze the leading ATPG algorithms and show how they can be used to ensure high fault coverage for SoC devices under test.
In Part III of this course, we will focus on BIST-the design methodology used to incorporate the tester into the device under test, thus allowing the device to test itself. BIST is gaining popularity in the SoC era because it affords considerable savings on the tester cost, and also allows the device to be tested at high-speed. Both MBIST (Memory BIST) and LBIST (Logic BIST) techniques will be analyzed. Finally, we will present the leading commercial CAD tools used to implement DFT, ATPG and BIST functions.
Intended Audience
This course is intended for IC, ASIC and systems design engineers, software and hardware developers, test and QA engineers, and managers in development, QA, test, and manufacturing.
Course Outline
Day 1
Day 2
DR. YACOUB ELZIQ is an SoC Senior Technologist & Entrepreneur. He has over 20 years technical and management experience working for computer system companies, ASIC manufacturers, and a founder his own businesses. His computer design experiences include Honeywell and Unisys and on the system side and Toshiba and VLSI technology on the chip side. His EDA (Electronic Design Automation) experience includes 5 years in designing and managing DFT, ATPG, and Chip planning products at Synopsys Inc. Dr. Elziq was the founder & CEO of XCAT, a hardware Verification acceleration startup that was acquired by Cadence, and a senior manager of Vertex corporation which was acquired by Toshiba. Dr. Elziq is a president/CEO of Jimzu Technologies, a SoC Consulting company, and also a Part-time Professor at Santa Clara University teaching graduate courses in both Hardware and Database designs.
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