This course introduces the student to the field of ASIC logic design using the IEEE standard Verilog HDL (Hardware Description Language). The course is divided into three parts: ASIC Design Overview, Verilog Modelling & Simulation, and Verilog Synthesis.

Part l: ASIC design methodology. Both logical and physical design flows are analyzed and then complemented with DFT (Design For Test) techniques and testersĘ interfaces.

Part II: Verilog language. This is presented and contrasted with other hardware and software languages, such as VHDL and C/C++. Then, the student learns how to create and simulate a small Verilog design. Three different modelling techniques used to practically design hardware are then presented using parts of industrial designs.

These are: Structural, Data Flow, and Behavioral Modelling. Both cycle-based and timing simulation of Verilog designs will be discussed. Modelling designs with variable delays, set-up and hold times, and pin-to-pin delays will be covered. In addition, Verilog transistor level capabilities for modelling and simulating full custom and structured custom designs will be presented. Also, cell- based library modelling using the Verilog UDP (Universal Design Primitive) will be introduced.

Part III: Verilog Synthesis. This involves the process of mapping the verified Verilog design into a technology specific netlist ready for layout. Only a subset of the Verilog language constructs can be used to implement a synthesizable design. We shall review such a subset and introduce the student to a set of proven Verilog coding techniques used by the leading EDA (Electronic Design Automation) synthesis tools to produce the most optimal design with minimal design iterations. Different industrial examples will be used to demonstrate such techniques.